1. Field of the Invention
The present invention relates to an apparatus, a processor and a method of controlling a cache memory.
2. Description of Related Art
A dynamic RAM (Dynamic Random Access Memory) usually used for a main storage device is increasing in its capacity more than ever. However, a speed of the dynamic RAM has not been increased as much as compared to an increase in speed of a processor. To make up the difference between speeds of a processor and a main storage device, a cache memory has been used. A cache memory employs a temporal/spatial locality of data and its replacement algorithm may be based on the temporal locality. The LRU (Least Recently Used) is one of the replacement algorithms based on temporal locality.
Circumstances are known in which a cache memory does not effectively work. A first example is that a processor plays-back stream data such as video data or audio data. Since stream data has low reusability and small temporal locality, a cache memory does not effectively work. A second example is that a program handles a large data set in the HPC (High Performance Computing) field, for example. When a program handles a large data set, various data stored in a cache memory is rewritten with the large data set due to the capacity limitation of the cache memory. As such, highly reusable data is replaced by the large data set, and the highly reusable data is no longer in the cache memory for the next opportunity.
FIG. 1 shows an example of a program used in the HPC field. In FIG. 1, assume that arrays A and B (e.g., A(I,J), B(I,J) in FIG. 1) constitute a data set of a capacity that may be registered in a single way of a cache memory and an array C (e.g., C(1,I,L,J) in FIG. 1) is a large data set.
In this case, after the arrays A and B are cached in a loop A, the array C being a large data set caches out most of the arrays A and B while a loop B is processed. If the cache memory may retain data in the arrays A and B, the data in the arrays A and B do not have to be transferred from a main storage device. Since data transferred from the main storage device is data in the array C (i.e., the data in the arrays A and B are already stored in the cache memory when the cache memory retains the data in the arrays A and B), the cache hit ratio improves and the processor performance improves. Additionally, the number of accesses to the main storage device decreases, thereby realizing the low power consumption.
Japanese Patent Laid-Open No. 2000-122968 (see Patent Document 1) discloses an input/output cache memory characterized by retaining data only for a particular input/output device, using a way of the input/output cache memory as a unit.
Japanese Patent Laid-Open No. 2002-140234 (see Patent Document 2) discloses a cache apparatus. The cache apparatus is placed between a processor and a main storage, and temporally registers data in the main storage by a data group unit in the main storage. The apparatus includes a cache memory, definition setting means, group determination means, registration policy designation means, reading out means, replacement decision means and registration means.
The cache memory registers control information of each retained data group in association with the data group. The definition setting means sets definition of attribution of a data group to be managed. The group determination means determines attribution of a data group to be fetched according to the definition being set from information of an instruction issued when the processor fetches a data group from the main storage. The registration policy designation means sets a registration policy defining how to register in the cache memory according to the attribution of the data group. The reading-out means determines whether or not a data group to be read from the processor has been recorded in the cache memory. In case of a miss, the reading-out means reads out the data group from the main storage. The replacement decision means decides replacement into the cache memory according to the attributes of the data group, attribution information in control information of the cache memory and the registration policy. The registration means registers a data group decided to be recorded by the replacement decision means in the cache memory, and registers the attribution as corresponding control information.
In Patent Document 2, the replacement decision means decides which way the data is to be replaced based on the registration policy. The registration policy defines a location (e.g., the way of the cache memory) of the cache memory that each of the data corresponding to each of the attribution information would be stored. In other words, the replacement decision means directly decides the location based on the registration policy. The registration policy is registered by the registration policy designation means which is configured by software or the like.
Japanese Patent Laid-Open No. 2004-110240 (see Patent Document 3) discloses a cache memory apparatus. In the cache memory apparatus, a cache memory includes a data memory region to temporally store data from a main memory based on an instruction by a processor, and a tag memory region to store an address of the temporally stored data. The cache memory includes a process information management table. The process information management table assigns an identification number and attributes including the residence priority in a cache to each process representing serial program execution and stores them as a table. The cache memory apparatus provides a field to designate an identification number of the above process correspondence in the above tag memory region. During the process execution, the apparatus uses a cache according to processing of designated attributes based on the above identification number.    [Patent Document 1] Japanese Patent Laid-Open No. 2000-122968    [Patent Document 2] Japanese Patent Laid-Open No. 2002-140234    [Patent Document 3] Japanese Patent Laid-Open No. 2004-110240